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FPAL15SL60
FPAL15SL60
Smart Power Module (SPM)
General Description
FPAL15SL60 is an advanced smart power module (SPM) that Fairchild has newly developed and designed to provide very compact and low cost, yet high performance ac motor drives mainly targeting low speed low-power inverter-driven application like air conditioners. It combines optimized circuit protection and drive matched to low-loss IGBTs. Highly effective short-circuit current detection/protection is realized through the use of advanced current sensing IGBT chips that allow continuous monitoring of the IGBTs current. System reliability is further enhanced by the built-in over-temperature and integrated under-voltage lock-out protection. The high speed built-in HVIC provides optocoupler-less IGBT gate driving capability that further reduce the overall size of the inverter system design. In addition the incorporated HVIC facilitates the use of single-supply drive topology enabling the FPAL15SL60 to be driven by only one drive supply voltage without negative bias.
Features
* UL Certified No. E209204 * 600V-15A 3-phase IGBT inverter bridge including control ICs for gate driving and protection * Single-grounded power supply due to built-in HVIC * Typical switching frequency of 3kHz * Built-in thermistor for over-temperature monitoring * Inverter power rating of 1kW / 100~253 Vac * Isolation rating of 2500Vrms/min. * Very low leakage current due to using ceramic substrate * Adjustable current protection level by varying series resistor value with sense-IGBTs
Applications
* AC 100V ~ 253V three-phase inverter drive for small power (1kW) ac motor drives * Home appliances applications requiring low switching frequency operation like air conditioners drive system * Application ratings: - Power : 1kW / 100~253 Vac - Switching frequency : Typical 3kHz (PWM Control) - 100% load current : 7.0A (Irms)
External View and Marking Information
Top View Bottom View
57 mm
55 mm
Marking
Device Name Version, Lot Code
Fig. 1.
(c)2002 Fairchild Semiconductor Corporation Rev. B1, February 2002
FPAL15SL60
Integrated Power Functions
* 600V-15A IGBT inverter for three-phase DC/AC power conversion (Please refer to Fig. 3)
Integrated Drive, Protection and System Control Functions
* For inverter high-side IGBTs: Gate drive circuit, High voltage isolated high-speed level shifting Control circuit under-voltage (UV) protection Note) Available bootstrap circuit example is given in Figs. 11, 16 and 17. * For inverter low-side IGBTs: Gate drive circuit, Short circuit protection (SC) Control supply circuit under-voltage (UV) protection * Temperature Monitoring: System over-temperature monitoring using built-in thermistor Note) Available temperature monitoring circuit is given in Fig. 17. * Fault signaling: Corresponding to a SC fault (Low-side IGBTs) or a UV fault (Low-side supply) * Input interface: 5V CMOS/LSTTL compatible, Schmitt trigger input
Pin Configuration
Top View
VS(U) VB(U) VCC(L) COM(L) IN(UL) IN(VL) IN(WL) VFO CFOD CSC RSC NC VTH RTH VCC(UH) IN(UH)
VS(V) VB(V) VCC(VH) IN(VH) COM(H) VS(W) VB(W) VCC(WH) IN(WH)
W
V
U
N
P
Fig. 2.
Pin Descriptions
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin Name VCC(L) COM(L) IN(UL) IN(VL) IN(WL) VFO CFOD CSC RSC NC VTH RTH W V U Pin Description Low-side Common Bias Voltage for IC and IGBTs Driving Low-side Common Supply Ground Signal Input Terminal for Low-side U Phase Signal Input Terminal for Low-side V Phase Signal Input Terminal for Low-side W Phase Fault Output Terminal Capacitor for Fault Output Duration Time Selection Capacitor (Low-pass Filter) for Short-current Detection Input Resistor for Short-circuit Current Detection NO Connection Thermistor Bias Voltage Series Resistor for the Use of Thermistor (Temperature Detection) Output Terminal for W Phase Output Terminal for V Phase Output Terminal for U Phase
(c)2002 Fairchild Semiconductor Corporation
Rev. B1, February 2002
FPAL15SL60
Pin Descriptions (Continued)
Pin Number 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin Name N P IN(WH) VCC(WH) VB(W) VS(W) COM(H) IN(VH) VCC(VH) VB(V) VS(V) IN(UH) VCC(UH) VB(U) VS(U) Pin Description Negative DC-Link Input Positive DC-Link Input Signal Input Terminal for High-side W Phase High-side Bias Voltage for W Phase IC High-side Bias Voltage for W Phase IGBT Driving High-side Bias Voltage Ground for W Phase IGBT Driving High-side Common Supply Ground Signal Input Terminal for High-side V Phase High-side Bias Voltage for V Phase IC High-side Bias Voltage for V Phase IGBT Driving High-side Bias Voltage Ground for V Phase IGBT Driving Signal Input Terminal for High-side U Phase High-side Bias Voltage for U Phase IC High-side Bias Voltage for U Phase IGBT Driving High-side Bias Voltage Ground for U Phase IGBT Driving
Internal Equivalent Circuit and Input/Output Pins
(29) VB(U) VB (1) VCC(L) (2) COM(L) (3) IN(UL) (4) IN(VL) (5) IN(WL) (6) VFO VCC COM(L) IN(UL) IN(VL) IN(WL) V(FO) Wout (7) CFOD (8) CSC (9) RSC (10) NC (11) VTH (12) RTH THERMISTOR C(FOD) C(SC) VB HO Vcc IN Vout Uout HO Vcc IN (28) VCC(UH) (27) IN(UH)
VS COM (30) VS(U) (25) VB(V) VB HO Vcc IN (24) VCC(VH) (23) IN(VH) (22) COM(H) (26) VS(V) (20) VB(W) (19) VCC(WH) (18) IN(WH)
VS COM
VS COM (21) VS(W)
W (13)
V (14)
U (15)
N (16)
P (17)
Note 1. Inverter low-side ( (1) - (12) pins) is composed of three sense-IGBTs including freewheeling diodes for each IGBT and one control IC which has gate driving, current sensing and protection functions. 2. Inverter power side ( (13) - (17) pins) is composed of two inverter dc-link input terminals and three inverter output terminals. 3. Inverter high-side ( (18) - (30) pins) is composed of three normal-IGBTs including freewheeling diodes and three drive ICs for each IGBT.
Fig. 3.
(c)2002 Fairchild Semiconductor Corporation
Rev. B1, February 2002
FPAL15SL60
Absolute Maximum Ratings
Inverter Part (TC = 25C,
Item Supply Voltage Supply Voltage (Surge) Collector-emitter Voltage Each IGBT Collector Current Each IGBT Collector Current (Peak) Collector Dissipation Operating Junction Temperature Unless Otherwise Specified) Symbol VDC VPN(Surge) VCES IC ICP PC TJ TC = 25C (Note Fig. 4) TC = 25C (Note Fig. 4) TC = 25C per One Chip (Note 1) Condition Applied to DC - Link Applied between P- N Rating 450 500 600 15 30 47 -55 ~ 150 Unit V V V A A W C
Note 1. It would be recommended that the average junction temperature should be limited to TJ 125C (@TC 100C) in order to guarantee safe operation.
Control Part (TC = 25C,
Item Control Supply Voltage
Unless Otherwise Specified) Symbol Condition Applied between VCC(H) - COM(H), VCC(L) - COM(L) VCC VBS VIN VFO IFO VSC Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) VS(W) Applied between IN(UH), IN(VH), IN(WH) - COM(H) IN(UL), IN(VL), IN(WL) - COM(L) Applied between VFO - COM(L) Sink Current at VFO Pin Applied between CSC - COM(L) Rating 18 20 -0.3 ~ 6.0 -0.3~VCC+0.5 5 -0.3~VCC+0.5 Unit V V V V mA V
High-side Control Bias Voltage Input Signal Voltage Fault Output Supply Voltage Fault Output Current Current Sensing Input Voltage
Total System
Item Self Protection Supply Voltage Limit (Short Circuit Protection Capability) Module Case Operation Temperature Storage Temperature Isolation Voltage Symbol Condition VPN(PROT) Applied to DC - Link, VCC = VBS = 13.5 ~ 16.5V TJ = 125C, Non-repetitive, less than 6s TC TSTG VISO 60Hz, Sinusoidal, AC 1 minute, Connection Pins to Heat-sink Plate Note Fig. 4 Rating 400 Unit V
-20 ~ 100 -55 ~ 150 2500
C C Vrms
(c)2002 Fairchild Semiconductor Corporation
Rev. B1, February 2002
FPAL15SL60
Case Temperature (TC) Detecting Point
VS(U) VB(U) VCC(L) COM IN(UL) IN(VL) IN(WL) VFO CFOD CSC RSC NC VTH RTH VCC(UH) IN(UH)
VS(V) VB(V) VCC(VH) IN(VH) COM VS(W) VB(W) VCC(WH) IN(WH)
Ceramic Substate
W
V
U
N
P
Fig. 4. Tc Measurement Point
(c)2002 Fairchild Semiconductor Corporation
Rev. B1, February 2002
FPAL15SL60
Absolute Maximum Ratings
Thermal Resistance
Item Junction to Case Thermal Resistance Symbol Condition Rth(j-c)Q Each IGBT under Inverter Operating Condition (Note 2) Rth(j-c)F Contact Thermal Resistance Rth(c-f) Each FWDi under Inverter Operating Condition (Note 2) Ceramic Substrate (per 1 Module) Thermal Grease Applied Min. Typ. Max. 2.61 3.73 0.06 Unit C/W C/W C/W
Note 2. For the measurement point of case temperature (Tc), please refer to Fig. 4.
Electrical Characteristics
Inverter Part (Tj = 25C, Unless Otherwise Specified)
Item Collector - emitter Saturation Voltage FWDi Forward Voltage Switching Times Symbol VCE(SAT) VCC = VBS = 15V VIN = 0V VFM tON tC(ON) tOFF tC(OFF) trr Collector - emitter Leakage Current ICES VIN = 5V Condition IC = 15A, Tj = 25C IC = 15A, Tj = 125C IC = 15A, Tj = 25C IC = 15A, Tj = 125C VPN = 300V, VCC = VBS = 15V IC = 15A, Tj = 25C VIN = 5V 0V, Inductive Load (High-Low Side) (Note 3) VCE = VCES, Tj = 25C Min. Typ. 0.39 0.12 1.0 0.6 0.1 Max. 2.3 2.4 2.5 2.3 250 Unit V V V V us us us us us uA
Note 3. tON and tOFF include the propagation delay time of the internal drive IC. tC(ON) and tC(OFF) are the switching time of IGBT itself under the given gate driving condition internally. For the detailed information, please see Fig. 5.
(c)2002 Fairchild Semiconductor Corporation
Rev. B1, February 2002
FPAL15SL60
t rr VCE
100% IC
IC
IC
VCE
V IN t ON
VIN(ON)
V IN
t C(ON)
90% IC 10% IC 10% VCE
t OFF
V IN(OFF)
tC(OFF)
10% VCE 10% IC
(a) Turn-on
(b) Turn-off
Fig. 5. Switching Time Definition
VCE : 100V/div.
IC : 5A/div.
IC : 5A/div.
VCE : 100V/div.
time : 100ns/div.
time : 200ns/div.
(a) Turn-on
(b) Turn-off
Fig. 6. Experimental Results of Switching Waveforms Test Condition: Vdc=300V, Vcc=15V, L=500uH (Inductive Load), TC=25C
(c)2002 Fairchild Semiconductor Corporation
Rev. B1, February 2002
FPAL15SL60
Electrical Characteristics
Control Part (Tj = 25C, Unless Otherwise Specified)
Item Control Supply Voltage High-side Bias Voltage Quiescent VCC Supply Current Symbol Condition Applied between VCC(H),VCC(L) - COM VCC VBS IQCCL IQCCH Quiescent VBS Supply Current Fault Output Voltage PWM Input Frequency Allowable Input Signal Blanking Time considering Leg Arm-short Short Circuit Trip Level Sensing Voltage of IGBT Current Supply Circuit UnderVoltage Protection IQBS VFOH VFOL fPWM tdead Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) - VS(W) VCC = 15V IN(UL, VL, WL) = 5V VCC = 15V IN(UH, VH, WH) = 5V VBS = 15V IN(UH, VH, WH) = 5V VCC(L) - COM(L) VCC(U), VCC(V), VCC(W) - COM(H) VB(U) - VS(U), VB(V) -VS(V), VB(W) - VS(W) Min. 13.5 13.5 4.5 3 Typ. Max. Unit 15 16.5 V 15 3 16.5 26 130 420 1.1 V mA uA uA V V kHz us
VSC = 0V, VFO Circuit: 4.7k to 5V Pull-up VSC = 1V, VFO Circuit: 4.7k to 5V Pull-up TC 100C, TJ 125C -20C TC 100C
VSC(ref) VSEN UVCCD UVCCR UVBSD UVBSR
TJ = 25, VCC = 15V (Note 4) -20C TC 100C, @ RSC = 82 and IC = 15A (Note Fig. 8) TJ 125C Detection Level Reset Level Detection Level Reset Level VCC = 15V, C(sc) = 1V CFOD = 33nF (Note 5) High-Side Low-Side Applied between IN(UH), IN(VH), IN(WH) - COM(H) Applied between IN(UL), IN(VL), IN(WL) - COM(L)
0.45 0.37 11.5 12 7.3 8.6 1.4 3.0 3.0 -
0.51 0.56 0.45 0.56 12 12.5 9.0 10.3 1.8 50 6.3 12.5 13 10.8 12 2.0 0.8 0.8 -
V V V V V V ms V V V V k k
Fault-out Pulse Width ON Threshold Voltage OFF Threshold Voltage ON Threshold Voltage OFF Threshold Voltage Resistance of Thermistor
tFOD VIN(ON) VIN(OFF) VIN(ON) VIN(OFF) RTH
@ TC = 25C (Note Figs. 4 and 7) @ TC = 80C (Note Figs. 4 and 7)
Note 4. Short-circuit current protection is functioning only at the low-sides. It would be recommended that the value of the external sensing resistor (RSC) should be selected around 56 in order to make the SC trip-level of about 20A. Please refer to Fig. 8 which shows the current sensing characteristics according to sensing resistor RSC. 5. The fault-out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation : CFOD = 18.3 x 10-6 x tFOD[F]
(c)2002 Fairchild Semiconductor Corporation
Rev. B1, February 2002
FPAL15SL60
R-T Curve
70
60
50
Resistance [k]
40
30
20
10
0 20
30
40
50
60
70
80
90
100
110
120
130
Temperature []
Fig. 7. R-T Curve of The Built-in Thermistor
90 80
SC Trip Current ISC [A]
70 60 50 40 30 20 10 10 20 30 40 50 60 70 80 90
Sensing Resistor RSC []
Fig. 8. Relationship between Sensing Resistor and SC Trip Current for Short-Circuit Protection (ISC = 82 x Rating Current(15A) / RSC)
(c)2002 Fairchild Semiconductor Corporation
Rev. B1, February 2002
FPAL15SL60
Mechanical Characteristics and Ratings
Item Mounting Torque Ceramic Flatness Weight Mounting Screw: M3 (Note 6 and 7) Condition Recommended 10Kg*cm Recommended 0.98N*m (Note Fig. 9) Limits Min. 8 0.78 0 Typ. 10 0.98 56 Max. 12 1.17 +100 Units Kg*cm N*m um g
Fig. 9. Flatness Measurement Position of The Ceramic Substrate
Note 6. Do not make over torque or mounting screws. Much mounting torque may cause ceramic cracks and bolts and Al heat-fin destruction. 7. Avoid one side tightening stress. Fig.10 shows the recommended torque order for mounting screws. Uneven mounting can cause the SPM ceramic substrate to be damaged.
4 1 3 2
Fig. 10. Mounting Screws Torque Order (1 2 3 4)
(c)2002 Fairchild Semiconductor Corporation
Rev. B1, February 2002
FPAL15SL60
Recommended Operating Conditions
Item Supply Voltage Control Supply Voltage High-side Bias Voltage Blanking Time for Preventing Arm-short PWM Input Signal Input ON Threshold Voltage Input OFF Threshold Voltage Symbol VPN VCC VBS tdead fPWM VIN(ON) VIN(OFF) Condition Applied between P - N Applied between VCC(H) - COM, VCC(L) - COM Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) - VS(W) For Each Input Signal TC 100C, TJ 125C Applied between UIN,VIN, WIN - COM Applied between UIN,VIN, WIN - COM Value Min. 13.5 13.5 3 Typ. 300 15 15 3 0 ~ 0.65 4 ~ 5.5 Max. 400 16.5 16.5 Unit V V V us kHz V V
ICs Internal Structure and Input/Output Conditions
RBS
15V Line
VCC(UH,VH,WH)
DBS
CBS
CBSC
VB(UH,VH,WH)
P
UV DETECT LEVEL SHIFT PULSE FILTER
5V Line
RP
CBP15
IN(UH,VH,WH) PULSE GENERATOR
R R SQ
CPH
COM
VS (UH,VH,WH)
HVIC
VCC(L)
LVIC
UV DETECT
BANDGAP REFERENCE TIME DELAY UV LATCH_UP
U,V,W
5V Line
RP
RPF
IN(UL,VL,WL)
UV PROTECTION
PULSE GENERATOR (HYSTERISIS)
BUFFER
SC PROTECTION SOFT_OFF CONTROL
OUTPUT
(UL,VL,WL)
VFO
CPL
CPF
CFOD
FAULT OUTPUT DURATION
SC LATCH_UP
TIME DELAY
SC DETECTION
CFOD
N
CSC RF RSC
Note 1. One LVIC drives three Sense-IGBTs and can do short-circuit current protection also. Three sense emitters are commonly connected to RSC terminal to detect short-circuit current. Low-side part of the inverter consists of three sense-IGBTs 2. One HVIC drives one normal-IGBT. High-side part of the inverter consists of three normal-IGBTs 3. Each IC has under voltage detection and protection function. 4. The logic input is compatible with standard CMOS or LSTTL outputs. 5. RPCP coupling at each input/output is recommended in order to prevent the gating input/output signals oscillation and it should be as close as possible to each SPM gating input pin. 6. It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics.
Fig. 11.
(c)2002 Fairchild Semiconductor Corporation
Rev. B1, February 2002
FPAL15SL60
Time Charts of SPMs Protective Function
Input Signal Internal IGBT Gate-Emitter Voltage Control Supply Voltage P3 P5 UV detect P1 P2 UV reset P6
Output Current Fault Output Signal P4
P1 : Normal operation - IGBT ON and conducting current P2 : Under voltage detection P3 : IGBT gate interrupt P4 : Fault signal generation P5 : Under voltage reset P6 : Normal operation - IGBT ON and conducting current
Fig. 12. Under-Voltage Protection (Low-side)
Input Signal Internal IGBT Gate-Emitter Voltage Control Supply Voltage VBS P3 P5 UV detect P1 P2 UV reset P6
Output Current Fault Output Signal
P4
P1 : Normal operation - IGBT ON and conducting current P2 : Under voltage detection P3 : IGBT gate interrupt P4 : No fault signal P5 : Under voltage reset P6 : Normal operation - IGBT ON and conducting current
Fig. 13. Under-Voltage Protection (High-side)
(c)2002 Fairchild Semiconductor Corporation
Rev. B1, February 2002
FPAL15SL60
P5 Input Signal Internal IGBT Gate-Emitter Voltage
SC Detection
P6
P1 P4 Output Current P2
SC Reference Voltage (0.5V) RC Filter Delay
P7
Sensing Voltage
Fault Output Signal
P3
P8
P1 : Normal operation - IGBT ON and conducting currents P2 : Short-circuit current detection P3 : IGBT gate interrupt / Fault signal generation P4 : IGBT is slowly turned off P5 : IGBT OFF signal P6 : IGBT ON signal - but IGBT cannot be turned on during the fault-output activation P7 : IGBT OFF state P8 : Fault-output reset and normal operation start
Fig. 14. Short-circuit Current Protection (Low-side Operation only)
5V-Line
FPAL15SL60
4.7k 100 100 100 VFO 1nF 1nF 0.47nF 1.2nF COM 4.7k 4.7k IN (UH) , IN (VH) , IN(WH) IN (UL) , IN (VL) , IN (WL)
CPU
Note It would be recommended that by-pass capacitors for the gating input signals, IN(XX) should be placed on the SPM pins and on the both sides of CPU and SPM for the fault output signal, VFO, as close as possible.
Fig. 15. Recommended CPU I/O Interface Circuit
(c)2002 Fairchild Semiconductor Corporation Rev. B1, February 2002
FPAL15SL60
15V-Line
One-leg Diagram of FPAL15SL60
P
20
Vcc VB HO
0.1uF 47uF
IN
COM VS
Vcc
Inverter Output
OUT
1000uF
0.1uF
IN COM
N
Fig. 16. Recommended Bootstrap Operation Circuit and Parameters
(c)2002 Fairchild Semiconductor Corporation
Rev. B1, February 2002
FPAL15SL60
Gating UL Gating VL Gating WL Fault CBPF
CPU
Gating UH Gating VH Gating WH RS R S RS
RS RS RS RS
V B(U) (29) 5V line (1) V CC(L) (2) COM(L) (3) IN (UL) (4) IN(VL) (5) IN(WL) IN (WL) (6) VFO V(FO) CPF CPL CPL CPL CFOD CSC RF 5V line RSC (7) CFOD (8) CSC (9) RSC (10) NC (11) VTH CSP05 CSPC05 RTH (12) RTH (13) W (14) V (15) U (16) N (17) P THERMISTOR Wout C(FOD) C(SC) VB HO Vcc IN VCC COM(L) IN(UL) IN (VL) Vout Uout VB(V) (25) VB HO Vcc IN V CC(VH) (24) IN(VH) (23) COM(H) (22) VS(V) (26) VB(W) (20) VCC(WH) (19) IN(WH) (18) VB HO Vcc IN VCC(UH) (28) IN(UH) (27)
DBS
RBS
5V line
RP CBSC CBS DBS RBS
RP
RP
VS COM V S(U) (30)
RP
RP
RP
RP
CPH CPH CPH
VS COM
CBSC CBS DBS RBS
15V line V S(W) (21) CBSC CBS CSPC15 CSP15
VS COM
Tem p. Monitoring
CDCS
M
Vdc +
Note 1. RPCPL/RPCPH coupling at each SPM input is recommended in order to prevent input signals' oscillation and it should be as close as possible to each SPM input pin. 2. By virtue of integrating an application specific type HVIC inside the SPM, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. 3. VFO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 4.7k resistance. Please refer to Fig. 15. 4. CSP15 of around 7 times larger than bootstrap capacitor CBS is recommended. 5. VFO output pulse width should be determined by connecting an external capacitor(CFOD) between CFOD(pin7) and COM(L)(pin2). (Example : if CFOD = 5.6 nF, then tFO = 300 s (typ.)) Please refer to the note 5 for calculation method. 6. Each input signal line should be pulled up to the 5V power supply with approximately 4.7k resistance (other RC coupling circuits at each input may be needed depending on the PWM control scheme used and on the wiring impedance of the system's printed circuit board). Approximately a 0.22~2nF by-pass capacitor should be used across each power supply connection terminals. 7. To prevent errors of the protection function, the wiring around RSC, RF and CSC should be as short as possible. 8. In the short-circuit protection circuit, please select the RFCSC time constant in the range 3~4 s. RF should be at least 30 times larger than RSC. (Recommended Example: RSC = 56 , RF = 3.9k and CSC = 1nF) 9. Each capacitor should be mounted as close to the pins of the SPM as possible. 10.To prevent surge destruction, the wiring between the smoothing capacitor and the P&N pins should be as short as possible. The use of a high frequency noninductive capacitor of around 0.1~0.22 uF between the P&N pins is recommended. 11.Relays are used at almost every systems of electrical equipments of home appliances. In these cases, there should be sufficient distance between the CPU and the relays. It is recommended that the distance be 5cm at least
Fig. 17. Application Circuit
(c)2002 Fairchild Semiconductor Corporation
Rev. B1, February 2002
FPAL15SL60
Detailed Package Outline Drawings
(c)2002 Fairchild Semiconductor Corporation
Rev. B1, February 2002
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM
FAST(R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM
OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench(R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SLIENT SWITCHER(R)
SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TruTranslationTM TinyLogicTM UHCTM UltraFET(R)
VCXTM
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be or (b) support or sustain life, or (c) whose failure to perform reasonably expected to cause the failure of the life support when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness. provided in the labeling, can be reasonably expected to result in significant injury to the user.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
(c)2002 Fairchild Semiconductor Corporation
Rev. H4

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